GitHub

Anuragshrestha9768/Assignment-1-FPGA

Implement an 8-bit Arithmetic Logic Unit (ALU) using Dataflow Modeling in Verilog Following Lab-1, which introduced basic Verilog syntax and structural modeling techniques, this assignment challenged ...
IEEE

Low Power Design Analysis of ALU Using FinFET

Abstract: This paper aims to provide a comparative analysis of low-power design methods for the implementation of the Arithmetic Logical Unit using Fin- Field Effective Transistor. The study evaluates ...
GitHub

Timing_Ideal.txt

0.28 0.28 ^ _337_/Y (sky130_fd_sc_hd__xnor2_1) 0.18 0.46 v _355_/Y (sky130_fd_sc_hd__o21ai_0) 0.40 0.86 v _368_/X (sky130_fd_sc_hd__maj3_1) 0.39 1.25 v _382_/X ...
IEEE

A High-Performance 64-Bit ALU for AI Applications Using Vedic Sutras and Adaptive Accuracy

Abstract: The Arithmetic Logic Unit, an important part of a processor, performs arithmetic as well as logic computations. The demand for better performance in processors has resulted in improved ...