GitHub

Low-Power-4-2-Priority-Encoder-Using-Positive-Feedback-Adiabatic-Logic-PFAL-

VLG pmos #(10) pmos_1(w4,w2,out1); // 2.0u 0.12u VLG pmos #(10) pmos_2(w6,w4,out1_bar); // 2.0u 0.12u VLG nmos #(10) nmos_3(w6,vss,out1_bar); // 1.0u 0.12u VLG nmos ...
IEEE

Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Network

Abstract: The automation of logic circuit design enhances chip performance, energy efficiency, and reliability, and is widely applied in the field of Electronic Design Automation (EDA). And-Inverter ...
GitHub

LogicDrawer - Interactive Digital Logic Circuit Designer

LogicDrawer is an interactive, web-based digital logic circuit designer and simulator. Perfect for students, educators, and engineers looking to design, simulate, and analyze digital circuits with ...
IEEE

High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller

Abstract: Cyclic redundancy check (CRC) and Forward error correction (FEC) encoding are widely used in high-speed information transceiver systems such as PCIe ...