IEEE

Characterization Methods of TMD Transistor Gate Dielectrics Targeting 1 nm EOT for 2-D CMOS Scaling

Abstract: 2-D materials show promise to possibly replace Si channel material to continue Moore’s Law scaling of transistors down to 5 nm gate lengths. The scaling opportunities of 2-D materials arise ...
IEEE

A Hierarchical-Hybrid Floating-Point Compute-in-Memory Macro Using FP-DAC and FP-ADC for Edge-AI Devices

Abstract: The floating-point (FP) format offers superior precision compared to its integer counterpart for multiply-and-accumulate (MAC) computations. With the rapid progress of artificial ...